Semiconductor device

ABSTRACT

A semiconductor device includes: a first electrode; a second electrode; and a dielectric layer stack positioned between the first electrode and the second electrode, the dielectric layer stack including a first anti-ferroelectric layer, a second anti-ferroelectric layer, and a ferroelectric layer between the first anti-ferroelectric layer and the second anti-ferroelectric.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation application of U.S. patentapplication Ser. No. 17/095,859 filed on Nov. 12, 2020, which claimspriority to Korean Patent Application No. 10-2020-0059084, filed on May18, 2020, which is incorporated herein by reference in its entirety.

BACKGROUND 1. Field

Various embodiments of the present invention relate generally to asemiconductor device and, more particularly, to an improvedsemiconductor device including both an anti-ferroelectric material and aferroelectric material.

2. Description of the Related Art

Sufficient capacitance has to be maintained to ensure sufficientoperation characteristics while further scaling down the size of acapacitor in a semiconductor device. One way to achieve this includesincreasing the dielectric constant of the dielectric material employedin the capacitor. However, known materials which are compatible withsemiconductor processing are limited, and therefore there are currentlylimits in scaling down the size of capacitors in a semiconductor devicewhile maintaining an effective capacitance.

SUMMARY

Embodiments of the present invention are directed to a semiconductordevice including a dielectric layer stack having a high dielectricconstant. The semiconductor device may include a capacitor.

In accordance with an embodiment of the present invention, asemiconductor device includes: a first electrode; a second electrode;and a dielectric layer stack positioned between the first electrode andthe second electrode, the dielectric layer stack including a firstanti-ferroelectric layer, a second anti-ferroelectric layer, and aferroelectric layer disposed between the first anti-ferroelectric layerand the second anti-ferroelectric.

In accordance with another embodiment of the present invention, asemiconductor device includes: a first electrode; a second electrode;and an alternating stack that is positioned between the first electrodeand the second electrode, the alternating stack including a plurality ofdielectric layer stacks and a plurality of leakage blocking layers thatare alternately stacked, wherein each of the dielectric layer stacksincludes a first anti-ferroelectric layer, a second anti-ferroelectriclayer, and a ferroelectric layer disposed between the firstanti-ferroelectric layer and the second anti-ferroelectric layer.

These and other features and advantages of the present invention willbecome understood by those having ordinary skill in the art of theinvention from the following figures and detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a semiconductor device in accordance with anembodiment of the present invention.

FIGS. 2A and 2B illustrate the polarization characteristics of aferroelectric and an anti-ferroelectric material respectively.

FIG. 2C illustrate the polarization characteristics of a stack includingboth a ferroelectric and an anti-ferroelectric material.

FIGS. 3 to 8B illustrate a semiconductor device in accordance with otherembodiments of the present invention.

FIGS. 9A to 9C are diagrams illustrating memory cells.

FIGS. 10A to 10F are diagrams illustrating application examples of acapacitor of a memory cell.

FIG. 11 is a cross-sectional view illustrating a semiconductor device inaccordance with another embodiment of the present invention.

DETAILED DESCRIPTION

Various embodiments of the present invention will be described below inmore detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in different forms and should not beconstrued as limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present invention tothose skilled in the art. Throughout the disclosure, like referencenumerals refer to like parts throughout the various figures andembodiments of the present invention.

The drawings are not necessarily to scale and in some instances,proportions may have been exaggerated in order to clearly illustratefeatures of the embodiments. When a first layer is referred to as being“on” a second layer or “on” a substrate, it not only refers to a casewhere the first layer is formed directly on the second layer or thesubstrate but also a case where a third layer exists between the firstlayer and the second layer or the substrate.

It will be further understood that when an element is referred to asbeing “connected to”, or “coupled to” another element, it may bedirectly on, connected to, or coupled to the other element, or one ormore intervening elements may be present. Furthermore, theconnection/coupling may not be limited to a physical connection but mayalso include a non-physical connection, e.g., a wireless connection.

In addition, it will also be understood that when an element is referredto as being “between” two elements, it may be the only element betweenthe two elements, or one or more intervening elements may also bepresent.

When a first element is referred to as being “over” a second element, itnot only refers to a case where the first element is formed directly onthe second element but also a case where a third element exists betweenthe first element and the second element.

It should be understood that the drawings are simplified schematicillustrations of the described devices and may not include well knowndetails for avoiding obscuring the features of the invention.

It should also be noted that features present in one embodiment may beused with one or more features of another embodiment without departingfrom the scope of the invention.

It is further noted, that in the various drawings, like referencenumbers designate like elements.

The composition of hafnium oxide (HfO₂) and zirconium oxide (ZrO₂) maybe adjusted to have ferroelectric characteristics or anti-ferroelectriccharacteristics. Accordingly, it is required to control polarizationswitching to occur at around the operation voltage of a volatile memorysuch as a Dynamic, Random-Access Memory (DRAM) and to use the dielectricconstant that is maximized in that area.

When a ferroelectric material is used, the coercive field, which is anoperation voltage, may be low, but even when the operation voltage isremoved (e.g., operation voltage is 0 V), the polarization does notbecome 0 and remnant polarization remains. This may restrict the use ofthe ferroelectric material for a DRAM.

When an anti-ferroelectric material is used, it is required to lower thecoercive field in order to use the DRAM because the coercive field inwhich polarization switching occurs is relatively large.

The dielectric material of a capacitor of a DRAM, according to anembodiment of the present invention provides a combination of the lowcoercive field (which is a characteristic of a ferroelectric material),no remnant polarization (which is a characteristic of ananti-ferroelectric material), and a high dielectric constant during apolarization switching operation (which is a common characteristics ofboth the ferroelectric material and the anti-ferroelectric material).

The dielectric constant of the ferroelectric material is largest in thevicinity of the coercive field. Some researchers are developing memorydevices using ferroelectric materials having a relatively low coercivefield. However, such devices may have problems because the polarizationdoes not become 0 at 0V and the remnant polarization remains. Thus,there is a limit in using a ferroelectric material in a volatile memory.On the other hand, the anti-ferroelectric material has a polarization of0 at 0V, but has a relatively high coercive field, which limits itsapplication to a volatile memory.

In the following embodiments of the present invention, a semiconductordevice including a stack structure is provided which employs both aferroelectric material and an anti-ferroelectric material. The stackstructure achieves a low switching voltage, that is, a low coercivefield, high capacitance, and no remnant polarization.

FIG. 1 illustrates a semiconductor device 100 in accordance with anembodiment of the present invention.

Referring to FIG. 1 , the semiconductor device 100 may be a portion of amemory. The semiconductor device 100 may be a portion of a volatilememory. The semiconductor device 100 may be a portion of DRAM. Thesemiconductor device 100 may include a DRAM capacitor.

The semiconductor device 100 may include a first electrode 101, a secondelectrode 102, and a dielectric layer stack 110 positioned between thefirst electrode 101 and the second electrode 102. The dielectric layerstack 110 may directly contact the first and the second electrodes 101,102.

The first electrode 101 may include a metal-containing material. Thefirst electrode 101 may include, for example, a metal a metal nitride, ametal carbide, a conductive metal nitride, a conductive metal oxide, orcombinations thereof. The first electrode 101 may include, for example,titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten(W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), rutheniumoxide (RuO₂), iridium oxide (IrO₂), niobium nitride (NbN), molybdenumnitride (MoN), or a combination thereof. According to another embodimentof the present invention, the first electrode 101 may include asilicon-containing material. The first electrode 101 may include, forexample, silicon, silicon germanium, or a combination thereof. Accordingto another embodiment of the present invention, the first electrode 101may include a stack of a metal-containing material and asilicon-containing material. The first electrode 101 may also bereferred to as ‘a bottom electrode’ or a storage node.

The second electrode 102 may include a silicon-containing material, agermanium-containing material, a metal-containing material, or acombination thereof. The second electrode 102 may include, for example,a metal, a metal nitride, a metal carbide, a conductive metal nitride, aconductive metal oxide, or a combination thereof. The second electrode102 may include, for example, titanium (Ti), titanium nitride (TiN),tantalum nitride (TaN), titanium carbon nitride (TiCN), tantalum carbonnitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru),iridium (Ir), ruthenium oxide (RuO₂), niobium nitride (NbN), molybdenumnitride (MoN), iridium oxide (IrO₂), silicon (Si), germanium (Ge),silicon germanium (SiGe), or a combination thereof. The second electrode102 may include ‘a Si/SiGe stack’ in which silicon germanium is stackedover silicon. In an embodiment, the second electrode 102 may include ‘aGe/SiGe stack’ in which silicon germanium is stacked over germanium. Inanother embodiment, the second electrode 102 may be formed by stackingsilicon germanium over a metal nitride. For example, the secondelectrode 102 may be formed by stacking silicon germanium (SiGe) overtitanium nitride (TiN). According to another embodiment of the presentinvention, the second electrode 102 may include titanium nitride (TiN),silicon germanium (SiGe), and tungsten (W) that are stacked in thementioned order. According to another embodiment of the presentinvention, the second electrode 102 may include titanium nitride (TiN),silicon germanium (SiGe), and tungsten nitride (WN) that are stacked inthe mentioned order.

The dielectric layer stack 110 may include at least one high-k materialhaving a high dielectric constant of approximately 7 or higher. Thehigh-k material may have a higher dielectric constant than silicon oxideand silicon nitride. The dielectric layer stack 110 may include at leastone ultra high-k material. The ultra high-k material may be a materialhaving a higher dielectric constant than the high-k material. The ultrahigh-k material may have a high dielectric constant of approximately 60or higher. The dielectric layer stack 110 may include at least oneferroelectric material and at least one anti-ferroelectric material.

The dielectric layer stack 110 may include a multi-layered stack ofdifferent dielectric materials. The dielectric layer stack 110 mayinclude a triple stack including a first dielectric layer 111, a seconddielectric layer 112, and a third dielectric layer 113. The thirddielectric layer 113 may be positioned between the first dielectriclayer 111 and the second dielectric layer 112. The first dielectriclayer 111, the second dielectric layer 112, and the third dielectriclayer 113 may be vertically arranged between the first electrode 101 andthe second electrode 102.

At least one among the first dielectric layer 111, the second dielectriclayer 112, and the third dielectric layer 113 may be a ferroelectricmaterial FE. For example, the third dielectric layer 113 may be aferroelectric material FE. The first dielectric layer 111 and the seconddielectric layer 112 may be materials that are different from the thirddielectric layer 113. The first dielectric layer 111 and the seconddielectric layer 112 may be the same material or different materials. Atleast one of the first dielectric layer 111 and the second dielectriclayer 112 may be anti-ferroelectric materials AFE. In the embodiment, ofFIG. 1 , both the first dielectric layer 111 and the second dielectriclayer 112 may be anti-ferroelectric materials AFE1, AFE2.

The first dielectric layer 111 may include a first anti-ferroelectricmaterial AFE1, and the second dielectric layer 112 may include, forexample, a second anti-ferroelectric material AFE2. The firstanti-ferroelectric material AFE1 and the second anti-ferroelectricmaterial AFE2 may be the same anti-ferroelectric material.Alternatively, the first anti-ferroelectric material AFE1 and the secondanti-ferroelectric material AFE2 may be different anti-ferroelectricmaterials. For example, the first anti-ferroelectric material AFE1 andthe second anti-ferroelectric material AFE2 may include, for example,(Hf) and zirconium (Zr). The first anti-ferroelectric material AFE1 andthe second anti-ferroelectric material AFE2 may be made of an oxideincluding hafnium (Hf) and zirconium (Zr). The first anti-ferroelectricmaterial AFE1 and the second anti-ferroelectric material AFE2 may bemade of a first hafnium zirconium oxide (HfZrO).

Other suitable materials for the first and second anti-ferroelectricmaterials AFE1 and AFE2 may include PbZrO₃, PbHfO₃, PbMgWO₃, PbZrTiO₃,BiNaTiO₃, NaNbO₃ or a combination thereof.

The third dielectric layer 113 may include a ferroelectric material FE.The ferroelectric material FE may include, for example, (Hf) andzirconium (Zr). The ferroelectric material FE may be made of an oxideincluding hafnium (Hf) and zirconium (Zr). The ferroelectric material FEmay include, for example, a second hafnium zirconium oxide (HfZrO).

Other suitable materials for the ferroelectric material FE may includeBaTiO₃, PbTiO₃, BiFeO₃, SrTiO₃, PbMgNdO₃, PbMgNbTiO₃, PbZrNbTiO₃,PbZrTiO₃, KNbO₃, LiNbO₃, GeTe, LiTaO₃, KNaNbO₃, BaSrTiO₃ andcombinations thereof.

The first anti-ferroelectric material AFE1 and the secondanti-ferroelectric material AFE2 may include a first hafnium zirconiumoxide, and the third dielectric layer 113 may include, for example, asecond hafnium zirconium oxide. The first hafnium zirconium oxide andthe second hafnium zirconium oxide may have different hafniumcomposition ratios. The first hafnium zirconium oxide and the secondhafnium zirconium oxide may have different zirconium composition ratios.The first hafnium zirconium oxide and the second hafnium zirconium oxidemay have different hafnium composition ratios and zirconium compositionratios.

The dielectric layer stack 110 of the semiconductor device 100 of FIG. 1may include a multi-layered stacked structure including a ferroelectricmaterial and an anti-ferroelectric material. A low coercive field may beobtained by the ferroelectric material FE, and no-remnant polarization(i.e. zero level of remaining polarization) may be maintained by thefirst and second anti-ferroelectric materials AFE1 and AFE2.

In the embodiment of FIG. 1 , forming the first and secondanti-ferroelectric materials AFE1 and AFE2 in direct contact with thefirst electrode 101 and the second electrode 102, respectively, allows,obtaining a polarization of ‘0’ when no voltage (0V) is applied betweenthe first electrode 101 and the second electrode 102. When the voltageapplied between the first electrode 101 and the second electrode 102 isgradually increased, a high dielectric constant may be secured as theferroelectric material FE begins switching first. Then, when the appliedvoltage is turned off (i.e., 0 V), the polarization becomes ‘0’ again(i.e., no remnant polarization), thus implementing an operation to avolatile memory.

The dielectric layer stack 110 may be referred to as ‘an AFE-FE-AFEstack’ because one ferroelectric material FE is positioned between twoanti-ferroelectric materials AFE1 and AFE2. The dielectric layer stack110 may have polarity-voltage characteristics with hysteresis loopsshowing two polarization characteristics (AFE-like and FE-like). Thehysteresis loop of the dielectric layer stack 110 may have a non-lineardirect contact point. Herein, the polarization of the non-linear directcontact point may be ‘0’.

FIG. 2A describes the polarity-voltage characteristics of aferroelectric material. FIG. 2B illustrates the polarity-voltagecharacteristics of an anti-ferroelectric material. FIG. 2C illustratesthe polarity-voltage characteristics of an AFE-FE-AFE stack.

Referring to FIG. 2A, the ferroelectric material FE may have a highcapacitance at a low voltage, but remnant polarization (Pr and −Pr) maybe present.

Referring to FIG. 2B, the anti-ferroelectric material AFE may have noremnant polarization (Pr), but it may have a low capacitance at a lowvoltage.

Referring to FIG. 2C, the AFE-FE-AFE stack may have polarity-voltagecharacteristics that exhibit two polarization characteristics (AFE-likeand FE-like). The hysteresis loop of the AFE-FE-AFE stack may have aferroelectric polarization (FE-like), an anti-ferroelectric polarization(AFE-like), and a non-linear direct contact point. Herein, when theapplied voltage is 0V, the non-linear direct contact point may have apolarization of ‘0’. In the anti-ferroelectric hysteresis loop of FIG.2B, a section in which polarization is ‘0’ may be linear.

Referring to FIG. 2C, it can be seen that the AFE-FE-AFE stack has ahigh capacitance at a low voltage and has the hysteresis loop with noremnant polarization.

FIG. 3 illustrates a semiconductor device in accordance with anotherembodiment of the present invention.

The constituent elements of the semiconductor device 200 shown in FIG. 2, except for the dielectric layer stack 120, may be the same as theconstituent elements of the semiconductor device 100 shown in FIG. 1 .Hereinafter, as for the descriptions of the first electrode and thesecond electrode, FIG. 1 will be referred to. The semiconductor device200 may be a portion of a memory. The semiconductor device 200 may be aportion of a volatile memory. The semiconductor device 200 may be aportion of a DRAM. The semiconductor device 200 may include a DRAMcapacitor.

Referring to FIG. 3 , the semiconductor device 200 may include a firstelectrode 101, a second electrode 102, and a dielectric layer stack 120between the first electrode 101 and the second electrode 102.

The dielectric layer stack 120 may include different hafnium zirconiumoxides that are stacked on one another. Here, the different hafniumzirconium oxides may have different hafnium composition ratios,different zirconium composition ratios, or different hafnium compositionratios and zirconium composition ratios. The different hafnium zirconiumoxides may have different thicknesses. The different hafnium zirconiumoxides may have different polarization characteristics. The hafniumzirconium oxide may include Hf_(x)Zr_(y)O (x>0, y>0, and x+y=1).

Hafnium zirconium oxide (Hf_(x)Zr_(y)O) may have a ferroelectriccharacteristic or an anti-ferroelectric characteristic according to theratio of the hafnium content (x) and the zirconium content (y). Theferroelectric hafnium zirconium oxide may have a hafnium content (x) offrom approximately 0.46 to approximately 0.75, and a zirconium content(y) of from approximately 0.25 to approximately 0.54. Theanti-ferroelectric hafnium zirconium oxide may have a hafnium content(x) of from approximately 0.2 to approximately 0.45 and a zirconiumcontent (y) of from approximately 0.55 to approximately 0.8.

The dielectric layer stack 120 may include a first hafnium zirconiumoxide (HZO1) 121, a second hafnium zirconium oxide (HZO2) 122, and athird hafnium zirconium oxide (HZO3) 123 between the first hafniumzirconium oxide 121 and the second hafnium zirconium oxide 122.Reference numerals HZO1, HZO2, and HZO3 may refer to Hf_(x)Zr_(y)O,individually.

The first hafnium zirconium oxide 121 and the third hafnium zirconiumoxide 123 may have different hafnium composition ratios. The firsthafnium zirconium oxide 121 and the third hafnium zirconium oxide 123may have different zirconium composition ratios. The first hafniumzirconium oxide 121 and the third hafnium zirconium oxide 123 may havedifferent hafnium composition ratios and different zirconium compositionratios. The first hafnium zirconium oxide 121 and the second hafniumzirconium oxide 122 may have the same hafnium composition ratio and thesame zirconium composition ratio.

The first hafnium zirconium oxide 121 may include Hf_(x)Zr_(y)O (x>0,y>0, x=0.46-0.75, y=0.25-0.54, x+y=1). In Hf_(x)Zr_(y)O, the hafniumcontent (x) and the zirconium content (y) may be the same. In oneexample, the hafnium content (x) may be 0.5, and the zirconium content(y) may be 0.5.

The second hafnium zirconium oxide 122 may include Hf_(x)Zr_(y)O (x>0,y>0, x=0.46-0.75, y=0.25-0.54, x+y=1). In the second hafnium zirconiumoxide 122 the hafnium content (x) and the zirconium content (y) may bethe same. For example, the ratio of the hafnium content (x) and thezirconium content (y) may be approximately 1:1. For example, the hafniumcontent (x) may be approximately 0.5, and the zirconium content (y) maybe approximately 0.5.

The third hafnium zirconium oxide 123 may include Hf_(x)Zr_(y)O (x>0,y>0, x=0.2-0.45, y=0.55-0.8, x+y=1, and y>x). In Hf_(x)Zr_(y)O, thehafnium content (x) may be smaller than the zirconium content (y). Forexample, the zirconium content (y) may be at least twice as much as thehafnium content (x). For example, the ratio of the zirconium content (y)and the hafnium content (x) may be approximately 2:1. As an example, thehafnium content (x) may be approximately 0.3, and the zirconium content(y) may be approximately 0.7. As such, a hafnium zirconium oxide havinga high zirconium content (y) may be referred to as a ‘zirconium(Zr)-rich hafnium zirconium oxide’ or a ‘zirconium oxide-rich hafniumzirconium oxide’. The third hafnium zirconium oxide 123 may have agreater zirconium content than the first and second hafnium zirconiumoxides 121 and 122.

The hafnium zirconium oxide (Hf_(x)Zr_(y)O) may have a ferroelectric FEcharacteristic or an anti-ferroelectric characteristic AFE based on thehafnium content (x) and the zirconium content (y). Also, a criticalthickness at which a change between the ferroelectric FE characteristicand the anti-ferroelectric characteristic AFE appears may differ basedon the hafnium content (x) and the zirconium content (y).

When the hafnium content (x) and the zirconium content (y) are the same,for example, Hf_(0.5)Zr_(0.5)O may have a ferroelectric characteristic.

When the zirconium content is greater than the hafnium content (i.e., azirconium-rich Hf_(x)Zr_(y)O), for example, Hf_(0.3)Zr_(0.7)O, it mayhave an anti-ferroelectric AFE characteristic.

Referring to FIG. 3 , the third hafnium zirconium oxide 123 having aferroelectric characteristic may be controlled to have a hafnium contentand a zirconium content in a ratio of 1:1, and the first and secondhafnium zirconium oxides having an anti-ferroelectric characteristic 121and 122 may be controlled to have the zirconium content and the hafniumcontent in a ratio of at least 2 times or more zirconium than hafnium(e.g., y/x at least equal to 2:1).

As the dielectric layer 123 is formed by controlling the composition ofthe zirconium content and the hafnium content in this way, apolarization-voltage curve may begin switching at a low voltage and thepolarization becomes ‘0’ again at ‘0 V’, thereby implementing anoperation as a volatile memory.

In the embodiment of FIG. 1 , the first and second dielectric layers111, 112, are in direct contact with the first and second electrodes 101and 102, respectively. Also, in the embodiment of FIG. 3 , the first andsecond hafnium zirconium oxides 121, 122 are in direct contact with thefirst and second electrodes 101 and 102, respectively.

FIG. 4 is a diagram for describing a semiconductor device in accordancewith another embodiment of the present invention. The semiconductordevice 300 of FIG. 4 may have the same constituent elements as thesemiconductor device 100 of FIG. 1 , except for an interface layer 331.Hereinafter, as for the detailed descriptions on the first electrode andthe second electrode, FIG. 1 and the description thereof may be referredto. The semiconductor device 300 may be a portion of a memory. Thesemiconductor device 300 may be a portion of a volatile memory. Thesemiconductor device 300 may be a portion of a DRAM. The semiconductordevice 300 may include a DRAM capacitor.

Referring to FIG. 4 , the semiconductor device 300 may include the firstelectrode 101, the second electrode 102, and a dielectric layer stack320 disposed between the first electrode 101 and the second electrode102. The semiconductor device 300 may further include an interface layer331 disposed between the second electrode 102 and the dielectric layerstack 320.

The dielectric layer stack 320 may include a multi-layer stack ofdifferent dielectric materials. The dielectric layer stack 320 may havea triple stack including a first anti-ferroelectric layer 321, a secondanti-ferroelectric layer 322, and a ferroelectric layer 323. Theferroelectric layer 323 may be positioned between the firstanti-ferroelectric layer 321 and the second anti-ferroelectric layer322.

The first anti-ferroelectric layer 321 and the second anti-ferroelectriclayer 322 may be made of the same anti-ferroelectric material ordifferent anti-ferroelectric materials. The first anti-ferroelectriclayer 321 and the second anti-ferroelectric layer 322 may include, forexample, (Hf) hafnium and zirconium (Zr). The first anti-ferroelectriclayer 321 and the second anti-ferroelectric layer 322 may be made of anoxide including hafnium (Hf) and zirconium (Zr). The firstanti-ferroelectric layer 321 and the second anti-ferroelectric layer 322may include zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). Thefirst anti-ferroelectric layer 321 and the second anti-ferroelectriclayer 322 may include zirconium-rich hafnium zirconium oxide (Zr-richHfZrO) having a zirconium content and a hafnium content in a ratio of2:1. Other suitable materials for the first and secondanti-ferroelectric layers 321 and 322 may include PbZrO₃, PbHfO₃,PbMgWO₃, PbZrTiO₃, BiNaTiO₃, NaNbO₃ and combinations thereof.

The ferroelectric layer 323 may include, for example, (Hf) hafnium andzirconium (Zr). The ferroelectric layer 323 may be made of an oxideincluding hafnium (Hf) and zirconium (Zr). The ferroelectric layer 323may include a hafnium zirconium oxide (HfZrO) having a zirconium contentand a hafnium content in a ratio of 1:1. Other suitable materials forthe ferroelectric layer 323 may include BaTiO₃, PbTiO₃, BiFeO₃, SrTiO₃,PbMgNdO₃, PbMgNbTiO₃, PbZrNbTiO₃, PbZrTiO₃, KNbO₃, LiNbO₃, GeTe, LiTaO₃,KNaNbO₃, BaSrTiO₃, combinations thereof.

The interface layer 331 may serve to suppress leakage current of thedielectric layer stack 320. The interface layer 331 may serve to protectthe dielectric layer stack 320 when the second electrode 102 is formed.The interface layer 331 may include a material that is reduced prior tothe dielectric layer stack 320 when the second electrode 102 is formed.The interface layer 331 may serve as a leakage current barrier having alarge effective work function (eWF) and a large conduction band offset(CBO). Also, the interface layer 331 may not increase the equivalentoxide film thickness T_(ox) of the dielectric layer stack 320. Theinterface layer 331 may serve as a portion of the second electrode 102.

The interface layer 331 may be a material having a largeelectronegativity. The interface layer 331 may have a larger Paulingelectronegativity than the dielectric layer stack 320. The interfacelayer 331 may include a material having a greater Paulingelectronegativity (which is, hereinafter, simply referred to as ‘anelectronegativity’) than the first and second anti-ferroelectric layers321 and 322, and the ferroelectric layer 323. The interface layer 301,may have a sufficiently large electronegativity so that it may be hardlyoxidized and readily reduced. Thus, the interface layer 331 may loseoxygen in place of the dielectric layer stack 320, and thus theinterface layer 331 may prevent oxygen loss of the dielectric layerstack 320.

The interface layer 331 may include atoms having a largeelectronegativity, for example, metal atoms, silicon atoms, or germaniumatoms. The interface layer 331 may include, for example, titanium (Ti),tantalum (Ta), aluminum (Al), tin (Sn), molybdenum (Mo), ruthenium (Ru),iridium (Ir), niobium (Nb), germanium (Ge), silicon (Si), nickel (Ni),or a combination thereof.

The interface layer 331 may include, for example, titanium oxide,tantalum oxide, niobium oxide, aluminum oxide, silicon oxide (SiO₂), tinoxide, germanium oxide, molybdenum dioxide, molybdenum trioxide, iridiumoxide, ruthenium oxide, nickel oxide, or a combination thereof.According to another embodiment of the present invention, the interfacelayer 331 may include a stack of molybdenum and molybdenum nitride(Mo/MoN) or a stack of tungsten and tungsten nitride (W/WN).

FIG. 5 is a diagram describing a semiconductor device 301 in accordancewith another embodiment of the present invention. The constituentelements of the semiconductor device 301 of FIG. 5 except for anadditional interface layer 332 may be the same as those of thesemiconductor device 300 shown in FIG. 4 . The semiconductor device 301may be a portion of a memory. The semiconductor device 301 may be aportion of a volatile memory. The semiconductor device 301 may be aportion of a DRAM. The semiconductor device 301 may include a DRAMcapacitor.

Referring to FIG. 5 , the semiconductor device 301 may include the firstelectrode 101, the second electrode 102, the dielectric layer stack 320disposed between the first electrode 101 and the second electrode 102,and the interface layer 331 between the second electrode 102 and thedielectric layer stack 320. The semiconductor device 301 may furtherinclude an additional interface layer 332 disposed between the firstelectrode 101 and the dielectric layer stack 320.

The dielectric layer stack 320 may include a multi-layer stack ofdifferent dielectric materials. The dielectric layer stack 320 mayinclude a triple stack including the first anti-ferroelectric layer 321,the second anti-ferroelectric layer 322, and the ferroelectric layer323. The ferroelectric layer 323 may be positioned between the firstanti-ferroelectric layer 321 and the second anti-ferroelectric layer322.

The first anti-ferroelectric layer 321 and the second anti-ferroelectriclayer 322 may be the same anti-ferroelectric material or differentanti-ferroelectric materials. The first anti-ferroelectric layer 321 andthe second anti-ferroelectric layer 322 may include, for example, (Hf)hafnium and zirconium (Zr). The first anti-ferroelectric layer 321 andthe second anti-ferroelectric layer 322 may be oxides including hafnium(Hf) and zirconium (Zr). The first anti-ferroelectric layer 321 and thesecond anti-ferroelectric layer 322 may include a zirconium-rich hafniumzirconium oxide (Zr-rich HfZrO). The first anti-ferroelectric layer 321and the second anti-ferroelectric layer 322 may include a zirconium-richhafnium zirconium oxide (Zr-rich HfZrO) having a zirconium content and ahafnium content in a ratio of zirconium to hafnium of approximately 2:1.Other suitable materials for the first and second anti-ferroelectriclayers 321 and 322 may include PbZrO₃, PbHfO₃, PbMgWO₃, PbZrTiO₃,BiNaTiO₃, NaNbO₃, and combinations thereof.

The ferroelectric layer 323 may include, for example, (Hf) hafnium andzirconium (Zr). The ferroelectric layer 323 may be made of an oxideincluding hafnium (Hf) and zirconium (Zr). The ferroelectric layer 323may include a hafnium zirconium oxide (HfZrO) having a zirconium contentand a hafnium content in a ratio of approximately 1:1. Other suitablematerials for the ferroelectric layer 323 may include BaTiO₃, PbTiO₃,BiFeO₃, SrTiO₃, PbMgNdO₃, PbMgNbTiO₃, PbZrNbTiO₃, PbZrTiO₃, KNbO₃,LiNbO₃, GeTe, LiTaO₃, KNaNbO₃, BaSrTiO₃, and combinations thereof

The interface layer 331 and the additional interface layer 332 may serveto suppress leakage current of the dielectric layer stack 320. Theinterface layer 331 may serve to protect the dielectric layer stack 320when the second electrode 102 is formed. The interface layer 331 mayinclude a material that is reduced prior to the dielectric layer stack320 when the second electrode 102 is formed. The interface layer 331 andthe additional interface layer 332 may function as a leakage currentbarrier having a large effective work function (eWF) and a largeconduction band offset (CBO). Also, the interface layer 331 and theadditional interface layer 332 may not increase the equivalent oxidefilm thickness T_(ox) of the dielectric layer stack 320. The interfacelayer 331 may serve as a portion of the second electrode 102.

The interface layer 331 and the additional interface layer 332 may bethe same material. The interface layer 331 and the additional interfacelayer 332 may have the same thickness. The interface layer 331 and theadditional interface layer 332 may be thinner than the first and secondanti-ferroelectric layers 321 and 322 and the ferroelectric layer 323.

The additional interface layer 332 may be a material having a largeelectronegativity. The additional interface layer 332 may have a largerPauling electronegativity than the dielectric layer stack 320. Theadditional interface layer 332 may include a material having a largerPauling electronegativity (which is, hereinafter, simply referred to as‘electronegativity’) than the first and second anti-ferroelectric layers321 and 322 and the ferroelectric layer 323. The additional interfacelayer 332 may have a sufficiently large electronegativity so that it maybe hardly oxidized and readily reduced.

The interface layer 331 and the additional interface layer 332 mayinclude atoms having a large electronegativity, such as metal atoms,silicon atoms, or germanium atoms. The interface layer 331 may include,for example, titanium (Ti), tantalum (Ta), aluminum (Al), tin (Sn),molybdenum (Mo), ruthenium (Ru), iridium (Ir), niobium (Nb), germanium(Ge), silicon (Si), nickel (Ni), or a combination thereof.

The interface layer 331 and the additional interface layer 332 mayinclude titanium oxide, tantalum oxide, niobium oxide, aluminum oxide,silicon oxide (SiO₂), tin oxide, germanium oxide, molybdenum dioxide,molybdenum trioxide, iridium oxide, ruthenium oxide, nickel oxide or acombination thereof. According to another embodiment of the presentinvention, the interface layer 331 may include a stack of molybdenum andmolybdenum nitride (Mo/MoN) or a stack of tungsten and tungsten nitride(W/WN).

FIG. 6 illustrates a semiconductor device 400 in accordance with anotherembodiment of the present invention. The semiconductor device 400 ofFIG. 6 may be similar to the semiconductor device 100 of FIG. 1 . Thesemiconductor device 400 may be a portion of a memory. The semiconductordevice 400 may be a portion of a volatile memory. The semiconductordevice 400 may be a portion of a DRAM. The semiconductor device 400 mayinclude a DRAM capacitor.

Referring to FIG. 6 , the semiconductor device 400 may include the firstelectrode 101, the second electrode 102, and a dielectric layer stack420 between the first electrode 101 and the second electrode 102.Hereinafter, as for detailed description on the first electrode 101 andthe second electrode 102, FIG. 1 and the description thereof may bereferred to.

The dielectric layer stack 420 may include at least oneanti-ferroelectric layer and at least one ferroelectric layer. Thedielectric layer stack 420 may include a first stack 420A and a secondstack 420B. The dielectric layer stack 420 may further include a highband gap layer 424 disposed between the first stack 420A and the secondstack 420B.

The stack 420A may include a multi-layer stack of different dielectricmaterials. The stack 420A may include a triple stack including a firstanti-ferroelectric layer 421, a second anti-ferroelectric layer 422, anda ferroelectric layer 423. The ferroelectric layer 423 may be positionedbetween the first anti-ferroelectric layer 421 and the secondanti-ferroelectric layer 422. The first anti-ferroelectric layer 421 andthe second anti-ferroelectric layer 422 may be the sameanti-ferroelectric material or different anti-ferroelectric materials.The first anti-ferroelectric layer 421 and the second anti-ferroelectriclayer 422 may include, for example, (Hf) hafnium and zirconium (Zr). Thefirst anti-ferroelectric layer 421 and the second anti-ferroelectriclayer 422 may be made of an oxide including hafnium (Hf) and zirconium(Zr). The first anti-ferroelectric layer 421 and the secondanti-ferroelectric layer 422 may include a zirconium-rich hafniumzirconium oxide (Zr-rich HfZrO). The first anti-ferroelectric layer 421and the second anti-ferroelectric layer 422 may include a zirconium-richhafnium zirconium oxide (Zr-rich HfZrO) having a zirconium content and ahafnium content of approximately 2:1. Other suitable materials for thefirst and second anti-ferroelectric layers 421 and 422 may includePbZrO₃, PbHfO₃, PbMgWO₃, PbZrTiO₃, BiNaTiO₃, NaNbO₃, and combinationsthereof. The ferroelectric layer 423 may include, for example, (Hf)hafnium and zirconium (Zr). The ferroelectric layer 423 may be made ofan oxide including hafnium (Hf) and zirconium (Zr). The ferroelectriclayer 423 may include a hafnium zirconium oxide (HfZrO) having azirconium content and a hafnium content at a ratio of approximately 1:1.Other suitable materials for the ferroelectric layer 423 may includeBaTiO₃, PbTiO₃, BiFeO₃, SrTiO₃, PbMgNdO₃, PbMgNbTiO₃, PbZrNbTiO₃,PbZrTiO₃, KNbO₃, LiNbO₃, GeTe, LiTaO₃, KNaNbO₃, BaSrTiO₃, andcombinations thereof

The second stack 420B may include a multi-layer stack of differentdielectric materials. The second stack 420B may include a triple stackincluding a first anti-ferroelectric layer 421′, a secondanti-ferroelectric layer 422′, and a ferroelectric layer 423′. Theferroelectric layer 423′ may be positioned between the firstanti-ferroelectric layer 421′ and the second anti-ferroelectric layer422′. The first anti-ferroelectric layer 421′ and the secondanti-ferroelectric layer 422′ may be the same anti-ferroelectricmaterial or different anti-ferroelectric materials. The firstanti-ferroelectric layer 421′ and the second anti-ferroelectric layer422′ may include, for example, (Hf) hafnium and zirconium (Zr). Thefirst anti-ferroelectric layer 421′ and the second anti-ferroelectriclayer 422′ may be made of an oxide including hafnium (Hf) and zirconium(Zr). The first anti-ferroelectric layer 421′ and the secondanti-ferroelectric layer 422′ may include a zirconium-rich hafniumzirconium oxide (Zr-rich HfZrO). The first anti-ferroelectric layer 421′and the second anti-ferroelectric layer 422′ may include azirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) having azirconium content and a hafnium content of approximately 2:1. Othersuitable materials for, the first and second anti-ferroelectric layers421′, 422′ may include PbZrO₃, PbHfO₃, PbMgWO₃, PbZrTiO₃, BiNaTiO₃ orNaNbO₃. The ferroelectric layer 423′ may include, for example, (Hf)hafnium and zirconium (Zr). The ferroelectric layer 423′ may be made ofan oxide including hafnium (Hf) and zirconium (Zr). The ferroelectriclayer 423′ may include a hafnium zirconium oxide (HfZrO) having azirconium content and a hafnium content of approximately 1:1. Othersuitable materials for the ferroelectric layer 423′ may include BaTiO₃,PbTiO₃, BiFeO₃, SrTiO₃, PbMgNdO₃, PbMgNbTiO₃, PbZrNbTiO₃, PbZrTiO₃,KNbO₃, LiNbO₃, GeTe, LiTaO₃, KNaNbO₃, BaSrTiO₃, and combinationsthereof.

The height (thickness) of the first stack 420A and the height(thickness) of the second stack 420B may be the same or different. Thefirst stack 420A and the second stack 420B may have the same structure.

In this embodiment, the first stack 420A and the second stack 420B mayeach have a triple stack structure including two anti-ferroelectriclayers and one ferroelectric layer. The first anti-ferroelectric layer421 of the first stack 420A and the first anti-ferroelectric layer 421′of the second stack 420B may be made of the same anti-ferroelectricmaterial or different anti-ferroelectric materials. The secondanti-ferroelectric layer 422 of the first stack 420A and the secondanti-ferroelectric layer 422′ of the second stack 420B may be made ofthe same anti-ferroelectric material or different anti-ferroelectricmaterials. The ferroelectric layer 423 of the first stack 420A and theferroelectric layer 423′ of the second stack 420B may be made of thesame ferroelectric material or different ferroelectric materials.

The first anti-ferroelectric layers 421 and 421′ and the secondanti-ferroelectric layers 422 and 422′ may include a zirconium-richhafnium zirconium oxide (Zr-rich HfZrO). The first anti-ferroelectriclayers 421 and 421′ and the second anti-ferroelectric layers 422 and422′ may include a zirconium-rich hafnium zirconium oxide (Zr-richHfZrO) having a zirconium content and a hafnium content at a ratio ofzirconium to hafnium of approximately 2:1. Other suitable materials forthe first anti-ferroelectric layers 421 and 421′ and the secondanti-ferroelectric layers 422 and 422′ may include PbZrO₃, PbHfO₃,PbMgWO₃, PbZrTiO₃, BiNaTiO₃, NaNbO₃, and combinations thereof. Theferroelectric layers 423 and 423′ may include a hafnium zirconium oxide(HfZrO) having a zirconium content and a hafnium content at a ratio ofapproximately 1:1. Other suitable materials for the ferroelectric layers423 and 423′ may include BaTiO₃, PbTiO₃, BiFeO₃, SrTiO₃, PbMgNdO₃,PbMgNbTiO₃, PbZrNbTiO₃, PbZrTiO₃, KNbO₃, LiNbO₃, GeTe, LiTaO₃, KNaNbO₃,BaSrTiO₃, and combinations thereof.

The high band gap layer 424 may serve to prevent leakage current of thedielectric layer stack 420. The high band gap layer 424 may include ahigh energy band gap material. The high band gap layer 424 may have anenergy band gap of from approximately 8.8 eV to approximately 10.6 eV.The high band gap layer 424 may include a material having a higherenergy band gap than the first stack 420A and the second stack 420B. Thehigh band gap layer 424 may include a material having a higher energyband gap than the first anti-ferroelectric layers 421 and 421′, thesecond anti-ferroelectric layers 422 and 422′, and the ferroelectriclayers 423 and 423′. The high band gap layer 424 may include a materialthat is different from the first stack 420A and the second stack 420B.The high band gap layer 424 may include a high-k material, but may havea lower dielectric constant than the first stack 420A and the secondstack 420B. The high band gap layer 424 may have a higher dielectricconstant than silicon oxide and silicon nitride. The high band gap layer424 may include aluminum oxide or beryllium oxide. The high band gaplayer 424 may be thinner than the first stack 420A and the second stack420B. Since the high band gap layer 424 has a relatively low dielectricconstant compared to the dielectric constant of the first stack 420A andthe second stack 420B, the high band gap layer 424 may be formed to beextremely thin to increase capacitance.

FIG. 7 illustrates a semiconductor device 401 in accordance with anotherembodiment of the present invention. The semiconductor device 401 ofFIG. 7 may be similar to the semiconductor device 400 of FIG. 6 . Thesemiconductor device 401 may be a portion of a memory. The semiconductordevice 401 may be a portion of a volatile memory. The semiconductordevice 401 may be a portion of a DRAM. The semiconductor device 401 mayinclude a DRAM capacitor.

Referring to FIG. 7 , the semiconductor device 401 may include the firstelectrode 101, the second electrode 102, and a dielectric layer stack420′ between the first electrode 101 and the second electrode 102.Hereinafter, as for the detailed descriptions on the first electrode 101and the second electrode 102, FIG. 1 and the description thereof may bereferred to.

The dielectric layer stack 420′ may include at least oneanti-ferroelectric layer and at least one ferroelectric layer. Thedielectric layer stack 420′ may include at least one triple stack TL andat least one high band gap layer HBG. The dielectric layer stack 420′may be formed by alternately stacking the triple stack TL and the highband gap layer HBG at least two or more times. Accordingly, thedielectric layer stack 420′ may be a stack including a plurality ofalternating triple stacks TL and high band gap layers HBG. The bottomtriple stack TL among the triple stacks TL may directly contact thefirst electrode 101, and the top triple stack TL among the triple stacksTL may directly contact the second electrode 102. The high band gaplayer HBG may not directly contact the first electrode 101 and thesecond electrode 102. According to another embodiment of the presentinvention, a high band gap layer HBG may be added between the top triplestack TL and the second electrode 102.

The triple stack TL may correspond to the first stack 420A or the secondstack 420B of FIG. 6 . The triple stack TL may have a structure in whicha ferroelectric layer is positioned between anti-ferroelectric layers.The high band gap layer HBG may correspond to the high band gap layer424 of FIG. 6 .

The triple stack TL may include a first anti-ferroelectric layer AFEL1,a second anti-ferroelectric layer AFEL2, and a ferroelectric layer FELdisposed between the first anti-ferroelectric layer AFEL1 and the secondanti-ferroelectric layer AFEL2. The first anti-ferroelectric layer AFEL1and the second anti-ferroelectric layer AFEL2 may be made of the sameanti-ferroelectric material or different anti-ferroelectric materials.The first anti-ferroelectric layer AFEL1 and the secondanti-ferroelectric layer AFEL2 may include, for example, (Hf) hafniumand zirconium (Zr). The first anti-ferroelectric layer AFEL1 and thesecond anti-ferroelectric layer AFEL2 may be made of an oxide includinghafnium (Hf) and zirconium (Zr). The first anti-ferroelectric layerAFEL1 and the second anti-ferroelectric layer AFEL2 may include azirconium-rich hafnium zirconium oxide (Zr-rich HfZrO). The firstanti-ferroelectric layer AFEL1 and the second anti-ferroelectric layerAFEL2 may include a zirconium-rich hafnium zirconium oxide (Zr-richHfZrO) having a zirconium content and a hafnium content at a ratio ofzirconium to hafnium at approximately 2:1. According to anotherembodiment of the present invention, the first and secondanti-ferroelectric layers AFEL1 and AFEL2 may be made of other suitablematerials including PbZrO₃, PbHfO₃, PbMgWO₃, PbZrTiO₃, BiNaTiO₃ NaNbO₃,and combinations thereof. The ferroelectric layer FEL may include, forexample, (Hf) hafnium and zirconium (Zr). The ferroelectric layer FELmay be made of an oxide including hafnium (Hf) and zirconium (Zr). Theferroelectric layer FEL may include a hafnium zirconium oxide (HfZrO)having a zirconium content and a hafnium content at a ratio ofapproximately 1:1. According to another embodiment of the presentinvention, the ferroelectric layer FEL may be made of other suitablematerials including BaTiO₃, PbTiO₃, BiFeO₃, SrTiO₃, PbMgNdO₃,PbMgNbTiO₃, PbZrNbTiO₃, PbZrTiO₃, KNbO₃, LiNbO₃, GeTe, LiTaO₃, KNaNbO₃,BaSrTiO₃, and combinations thereof

The high band gap layer HBG may serve to prevent the leakage current ofthe dielectric layer stack 420′. The high band gap layer HBG may includea high energy band gap material. The high band gap layer HBG may have anenergy band gap of from approximately 8.8 eV to approximately 10.6 eV.The high band gap layer HBG may include a material having a higherenergy band gap than the triple stack TL. The high band gap layer HBGmay include a material having a higher energy band gap than the firstand second anti-ferroelectric layers AFEL1 and AFEL2 and theferroelectric layer FEL. The high band gap layer HBG may include amaterial that is different from the triple stack TL. The high band gaplayer HBG may include a high-k material, but may have a lower dielectricconstant than the triple stack TL. The high band gap layer HBG may havea higher dielectric constant than silicon oxide and silicon nitride. Thehigh band gap layer HBG may include aluminum oxide or beryllium oxide.The high band gap layer HBG may be thinner than the triple stack TL.Since the high band gap layer HBG has a relatively lower dielectricconstant than the triple stack TL, the high band gap layer HBG may beformed to be extremely thin to increase capacitance.

FIGS. 8A and 8B illustrate semiconductor devices in accordance withother embodiments of the present invention. The semiconductor device 402of FIG. 8A and the semiconductor device 403 of FIG. 8B may be similar tothe semiconductor device 400 of FIG. 6. Each of the semiconductordevices 402 and 403 may be a portion of the memory. Each of thesemiconductor devices 402 and 403 may be a portion of a volatile memory.Each of the semiconductor devices 402 and 403 may be a portion of aDRAM. Each of the semiconductor devices 402 and 403 may include a DRAMcapacitor.

Referring to FIG. 8A, the semiconductor device 402 may include the firstelectrode 101, the second electrode 102, the dielectric layer stack 420between the first electrode 101 and the second electrode 102, and aninterface layer 431 between the second electrode 102 and the dielectriclayer stack 420.

The dielectric layer stack 420 may include the first stack 420A, thesecond stack 420B, and the high band gap layer 424 disposed between thefirst stack 420A and the second stack 420B. The first stack 420A mayinclude the first anti-ferroelectric layer 421, the secondanti-ferroelectric layer 422, and the ferroelectric layer 423 disposedbetween the first anti-ferroelectric layer 421 and the secondanti-ferroelectric layer 422. The second stack 420B may include thefirst anti-ferroelectric layer 421′, the second anti-ferroelectric layer422′, and the ferroelectric layer 423′ disposed between the firstanti-ferroelectric layer 421′ and the second anti-ferroelectric layer422′.

Hereinafter, detailed descriptions on the first electrode 101, thesecond electrode 102, and the dielectric layer stack 420 will bedescribed with reference to the above-described embodiments of thepresent invention.

The interface layer 431 may correspond to the interface layer 331 ofFIG. 4 .

The interface layer 431 may be positioned between the second stack 420Band the second electrode 102. The interface layer 431 may be a materialhaving a large electronegativity. The interface layer 431 may have ahigher Pauling Electronegativity than the dielectric layer stack 420.The interface layer 431 may include a material having a largerelectronegativity than the first anti-ferroelectric layers 421 and 421′,the second anti-ferroelectric layers 422 and 422′, and the ferroelectriclayers 423 and 423′. Accordingly, the interface layer 431 may preventoxygen loss of the dielectric layer stack 420.

The interface layer 431 may include atoms having largeelectronegativity, such as metal atoms, silicon atoms, or germaniumatoms. The interface layer 431 may include, for example, titanium (Ti),tantalum (Ta), aluminum (Al), tin (Sn), molybdenum (Mo), ruthenium (Ru),iridium (Ir), niobium (Nb), germanium (Ge), silicon (Si), nickel (Ni),or a combination thereof.

The interface layer 431 may include titanium oxide, tantalum oxide,niobium oxide, aluminum oxide, silicon oxide (SiO₂), tin oxide,germanium oxide, molybdenum dioxide, molybdenum trioxide, iridium oxide,ruthenium oxide, nickel oxide or a combination thereof. According toanother embodiment of the present invention, the interface layer 431 mayinclude a stack of molybdenum and molybdenum nitride (Mo/MoN) or a stackof tungsten and tungsten nitride (W/WN).

The semiconductor device 403 of FIG. 8B may have the same constituentelements as those of the semiconductor device 402 of FIG. 8A, except foran additional interface layer 432.

The semiconductor device 403 may include the first electrode 101, thesecond electrode 102, the dielectric layer stack 420 disposed betweenthe first electrode 101 and the second electrode 102, the interfacelayer 431 between the second electrode 102 and the dielectric layerstack 420, and an additional interface layer 432 disposed between thefirst electrode 101 and the dielectric layer stack 420.

The additional interface layer 432 and the interface layer 431 may serveto suppress leakage current of the dielectric layer stack 420. Theinterface layer 431 may serve to protect the dielectric layer stack 420when the second electrode 102 is formed. The interface layer 431 mayinclude a material that is reduced prior to the dielectric layer stack420 when the second electrode 102 is formed. The interface layer 431 andthe additional interface layer 432 may serve as a large leakage currentbarrier having a large effective work function (eWF) and a largeconduction band offset (CBO). Also, the interface layer 431 and theadditional interface layer 432 may not increase the equivalent oxidefilm thickness T_(ox) of the dielectric layer stack 420. The interfacelayer 431 may serve as a portion of the second electrode 102.

The interface layer 431 and the additional interface layer 432 may bemade of the same material. The interface layer 431 and the additionalinterface layer 432 may have the same thickness. The interface layer 431and the additional interface layer 432 may be thinner than the first andsecond anti-ferroelectric layers 421 and 422 and the ferroelectric layer423.

The additional interface layer 432 may be a material having a largeelectronegativity. The additional interface layer 432 may have a largerPauling electronegativity than the dielectric layer stack 420. Theadditional interface layer 432 may include a material having a greaterelectronegativity than the first anti-ferroelectric layers 421 and 421′,the second anti-ferroelectric layers 422 and 422′, and the ferroelectriclayers 423 and 423′.

The additional interface layer 432 may include atoms having a largeelectronegativity, such as metal atoms, silicon atoms, or germaniumatoms. The interface layer 331 may include, for example, titanium (Ti),tantalum (Ta), aluminum (Al), tin (Sn), molybdenum (Mo), ruthenium (Ru),iridium (Ir), niobium (Nb), germanium (Ge), silicon (Si), nickel (Ni),or a combination thereof.

The additional interface layer 432 may include titanium oxide, tantalumoxide, niobium oxide, aluminum oxide, silicon oxide (SiO₂), tin oxide,germanium oxide, molybdenum dioxide, molybdenum trioxide, iridium oxide,ruthenium oxide, nickel oxide, or a combination thereof.

According to another embodiment of the present invention, the dielectriclayer stack 420 of the semiconductor devices 402 and 403 may be replacedwith an alternating stack corresponding to the dielectric layer stack420′ of FIG. 7 .

FIGS. 9A to 9C are diagrams illustrating memory cells. FIG. 9B is across-sectional view taken along a line A-A′ in FIG. 9A. FIG. 9C is across-sectional view taken along a line B-B′ in FIG. 9A.

The memory cell 500 may include a cell transistor including a buriedword line 508, a bit line 514, and a capacitor 600. The capacitor 600may include a dielectric layer stack, and the dielectric layer stack mayinclude one among the dielectric layer stacks of the above-describedembodiments of the present invention.

The memory cell 500 will now be described in detail.

An isolation layer 503 and an active region 504 may be formed over thesubstrate 501. A plurality of active regions 504 may be defined by theisolation layer 503. The substrate 501 may be a material appropriate forsemiconductor processing. The substrate 501 may include a semiconductorsubstrate. The substrate 501 may be formed of a material containingsilicon. The substrate 501 may include, for example, silicon,monocrystalline silicon, polysilicon, amorphous silicon, silicongermanium, monocrystalline silicon germanium, polycrystalline silicongermanium, carbon-doped silicon, combinations thereof, or multi-layersthereof. The substrate 501 may also include other semiconductormaterials, such as germanium. The substrate 501 may include agroup-III/V semiconductor substrate, for example, a compoundsemiconductor substrate, such as GaAs. The substrate 501 may include aSilicon On Insulator (SOI) substrate. The isolation layer 503 may beformed in an isolation trench 502 by a Shallow Trench Isolation (STI)process.

A word line trench 506 may be formed in the substrate 501. The word linetrench 506 may be referred to as a gate trench. A gate dielectric layer507 may be formed on the surface of the word line trench 506. A buriedword line 508 partially filling the word line trench 506 may be formedover the gate dielectric layer 507. The buried word line 508 may bereferred to as a buried gate electrode. A word line capping layer 509may be formed over the buried word line 508. The top surface of theburied word line 508 may be positioned at a lower level than the surfaceof the substrate 501. The buried word line 508 may be made of a lowresistance metal material. The buried word line 508 may be made of astack in which titanium nitride and tungsten are sequentially stacked.According to another embodiment of the present invention, the buriedword line 508 may be formed of titanium nitride only (TiN Only).

First and second impurity regions 510 and 511 may be formed in thesubstrate 501. The first and second impurity regions 510 and 511 may bespaced apart from each other by the word line trench 506. The first andsecond impurity regions 510 and 511 may be referred to as first andsecond source/drain regions. The first and second impurity regions 510and 511 may include an N-type impurity such as arsenic (As) orphosphorus (P). Accordingly, the buried word line 508 and the first andsecond impurity regions 510 and 511 may become a cell transistor. Thecell transistor may improve a short channel effect by the buried wordline 508.

A bit line contact plug 513 may be formed over the substrate 501. Thebit line contact plug 513 may be coupled to the first impurity region510. The bit line contact plug 513 may be positioned in a bit linecontact hole 512. The bit line contact hole 512 may be formed using thehard mask layer 505. The hard mask layer 505 may be formed over thesubstrate 501. The bit line contact hole 512 may expose the firstimpurity region 510. The bottom surface of the bit line contact plug 513may be lower than the top surface of the substrate 501. The bit linecontact plug 513 may be formed, for example, of polysilicon or a metalmaterial. A portion of the bit line contact plug 513 may have a linewidth which is smaller than the diameter of the bit line contact hole512. A bit line 514 may be formed over the bit line contact plug 513. Abit line hard mask 515 may be formed over the bit line 514. The stackedstructure of the bit line 514 and the bit line hard mask 515 may bereferred to as a bit line structure BL. The bit line 514 may have a lineshape extending in a direction intersecting with the buried word line508. A portion of the bit line 514 may be coupled to the bit linecontact plug 513. The bit line 514 may include a metal material. The bitline hard mask 515 may include a dielectric material.

A bit liner spacer 516 may be formed on a sidewall of the bit linestructure BL. The bottom portion of the bit liner spacer 516 may extendto be formed on both sides of the bit line contact plug 513. The bitliner spacer 516 may include, for example, silicon oxide, siliconnitride, or a combination thereof. According to another embodiment ofthe present invention, the bit liner spacer 516 may include an air gap.For example, it may be a NAN (Nitride-Air gap-Nitride) structure inwhich an air gap is positioned between silicon nitrides.

A storage node contact plug SNC may be formed between the neighboringbit line structures BL. The storage node contact plug SNC may be formedin a storage node contact hole 518. The storage node contact plug SNCmay be coupled to the second impurity region 511. The storage nodecontact plug SNC may include a lower plug 519 and an upper plug 521. Thestorage node contact plug SNC may further include an ohmic contact layer520 disposed between the lower plug 519 and the upper plug 521. Theohmic contact layer 520 may include a metal silicide. The upper plug 521may include a metal material, and the lower plug 519 may include asilicon-containing material.

From the perspective of a direction parallel to the bit line structureBL, a plug isolation layer 517 may be formed between the neighboringstorage node contact plugs SNCs. The plug isolation layer 517 may beformed between the neighboring bit line structures BL and may provide astorage node contact hole 518 together with the hard mask layer 505.

The capacitor 600 may be coupled to the storage node contact plug SNC.

FIGS. 10A to 10F are diagrams illustrating application examples of thecapacitor 600 of a memory cell. Hereinafter, the lower electrodes 601,601P, and 601L may correspond to the first electrode 101 of theabove-described embodiments of the present invention, and the upperelectrode 602 may correspond to the second electrode 102.

Referring to FIG. 10A, a capacitor 611 may include a lower electrode601, a dielectric layer stack 603, and an upper electrode 602. The lowerelectrode 601 may have a cylindrical shape. The dielectric layer stack603 may correspond to one among the dielectric layer stacks of theabove-described embodiments. Accordingly, the dielectric layer stack 603may include a first anti-ferroelectric layer, a secondanti-ferroelectric layer, and a ferroelectric layer disposed between thefirst anti-ferroelectric layer and the second anti-ferroelectric layer.The dielectric layer stack 603 may include, for example, twozirconium-rich hafnium zirconium oxide layers and one hafnium zirconiumoxide layer. The two zirconium-rich hafnium zirconium oxide layers mayinclude a zirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) havinga zirconium content and a hafnium content at a ratio of zirconium tohafnium of approximately 2:1. One hafnium zirconium oxide layer mayinclude a hafnium zirconium oxide having a zirconium content and ahafnium content at a ratio of approximately 1:1.

Hereinafter, detailed descriptions on the parts of FIGS. 10B to 10Foverlapping with those of the embodiment of FIG. 10A may be omitted.

Referring to FIG. 10B, a capacitor 612 may include a lower electrode601, a dielectric layer stack 603, and an upper electrode 602 that areformed in a cylinder shape. The capacitor 612 may further include asupporter 600S. The supporter 600S may be a structure that supports theouter wall of the lower electrode 601. The supporter 600S may include,for example, silicon nitride. According to another embodiment of thepresent invention, a multi-level supporter formed of a plurality ofsupporters 600S may support the lower electrode 601. For example, themulti-level supporter may be a two-level supporter structure formed of alower-level supporter and an upper-level supporter. Also, themulti-level supporter may be a three-level supporter structure formed ofa lower-level supporter, a middle-level supporter, and an upper-levelsupporter.

Referring to FIGS. 10C and 10D, capacitors 613 and 614 may include alower electrode 601P, a dielectric layer stack 603, and an upperelectrode 602 with the lower electrode having a pillar shape. Thecapacitor 614 of FIG. 10D may further include a supporter 600S.

Referring to FIGS. 10E and 10F, capacitors 615 and 616 may include alower electrode 601L, a dielectric layer stack 603, and an upperelectrode 602 with the lower electrode having a pillar shape (FIG. 10E)or a hybrid pillar-cylinder shape (FIG. 10F). The capacitor 616 of FIG.10F may further include a supporter 600S. The lower electrode 601L maybe a hybrid structure in which a pillar shape and a cylinder shape aremerged. More specifically, the lower electrode 601L may have a lowerpart that has pillar shape and an upper part which has a cylinder shape.This hybrid structure of a pillar shape and a cylinder shape may bereferred to simply as a hybrid pillar-cylinder shape. In an embodiment,the supporter 600S may be in contact with the cylinder part of the lowerelectrode 601L.

The dielectric layer stack in accordance with the above-describedembodiments of the present invention may be applied to a peripheralcircuit of a DRAM. For example, the DRAM may include a memory cellregion including memory cells (500 in FIG. 9A) and a peripheral circuitregion including a peripheral transistor. The gate dielectric layer ofthe peripheral transistor may include one among the dielectric layerstacks of the above-described embodiments of the present invention. Forexample, the gate dielectric layer of the peripheral transistor mayinclude a first anti-ferroelectric layer, a second anti-ferroelectriclayer, and a ferroelectric layer between the first anti-ferroelectriclayer and the second anti-ferroelectric layer. The gate dielectric layerof the peripheral transistor may include two zirconium-rich hafniumzirconium oxide layers and one hafnium zirconium oxide layer. The twozirconium-rich hafnium zirconium oxide layers may include azirconium-rich hafnium zirconium oxide (Zr-rich HfZrO) having azirconium content and a hafnium content at a ratio of zirconium tohafnium of approximately 2:1. One hafnium zirconium oxide layer mayinclude a hafnium zirconium oxide having a zirconium content and ahafnium content at a ratio of approximately 1:1.

FIG. 11 is a cross-sectional view illustrating a semiconductor device inaccordance with another embodiment of the present invention.

Referring to FIG. 11 , the semiconductor device 700 may include atransistor. The semiconductor device 700 may include a semiconductorsubstrate 701, a gate dielectric layer 710, a gate electrode 720, asource region 740, and a drain region 750. The gate dielectric layer 710may be formed over the semiconductor substrate 701, and the gateelectrode 720 may be formed over the gate dielectric layer 710. Thesource region 740 and the drain region 750 may be formed in thesemiconductor substrate 701.

The gate dielectric layer 710 may include one among the dielectric layerstacks in accordance with the above-described embodiments of the presentinvention. In this embodiment, the gate dielectric layer 710 may be atriple stack including a first anti-ferroelectric layer 711, a secondanti-ferroelectric layer 712, and a ferroelectric layer 713 disposedbetween the first anti-ferroelectric layer 711 and the secondanti-ferroelectric layer 712. The first anti-ferroelectric layer 711 andthe second anti-ferroelectric layer 712 may be made of the sameanti-ferroelectric material or different anti-ferroelectric materials.The first anti-ferroelectric layer 711 and the second anti-ferroelectriclayer 712 may include, for example, (Hf) hafnium and zirconium (Zr). Thefirst anti-ferroelectric layer 711 and the second anti-ferroelectriclayer 712 may be made of an oxide including hafnium (Hf) and zirconium(Zr). The first anti-ferroelectric layer 711 and the secondanti-ferroelectric layer 712 may include a zirconium-rich hafniumzirconium oxide (Zr-rich HfZrO). The first anti-ferroelectric layer 711and the second anti-ferroelectric layer 712 may include a zirconium-richhafnium zirconium oxide (Zr-rich HfZrO) having a zirconium content and ahafnium content of approximately 2:1. Other suitable materials for thefirst and second anti-ferroelectric layers 711 and 712 may includePbZrO₃, PbHfO₃, PbMgWO₃, PbZrTiO₃, BiNaTiO₃, NaNbO₃, and combinationsthereof. The ferroelectric layer 713 may include, for example, (Hf)hafnium and zirconium (Zr). The ferroelectric layer 713 may be made ofan oxide including hafnium (Hf) and zirconium (Zr). The ferroelectriclayer 713 may include a hafnium zirconium oxide (HfZrO) having azirconium content and a hafnium content at a ratio of approximately 1:1.Other suitable materials for the ferroelectric layer 713 may includeBaTiO₃, PbTiO₃, BiFeO₃, SrTiO₃, PbMgNdO₃, PbMgNbTiO₃, PbZrNbTiO₃,PbZrTiO₃, KNbO₃, LiNbO₃, GeTe, LiTaO₃, KNaNbO₃, BaSrTiO₃, andcombinations thereof.

The gate electrode 720 may be a metal gate electrode including ametal-based material. The gate electrode 720 may include, for example,tungsten, aluminum, tungsten nitride, titanium nitride, titanium, or acombination thereof.

The source region 740 and the drain region 750 may include an impurityof the same conductive type. The source region 740 and the drain region750 may include an N-type impurity or a P-type impurity. The N-typeimpurity may include, for example, phosphorus or arsenic, and the P-typeimpurity may include boron or indium.

According to another embodiment of the present invention, a thininterface layer may be further formed between the gate dielectric layer710 and the semiconductor substrate 701. The thin interface layer mayinclude, for example, silicon oxide or silicon oxynitride.

According to another embodiment of the present invention, the gatedielectric layer 710 may be applied to the gate dielectric layer of aFinFET.

The dielectric layer stack in accordance with the above-describedembodiments of the present invention may be applied to ametal-insulator-metal (MIM) capacitor. For example, the MIM capacitormay include a first metal electrode, a second metal electrode, and adielectric layer stack formed between the first metal electrode and thesecond metal electrode. The dielectric layer stack of the MIM capacitormay include one among the dielectric layer stacks of the above-describedembodiments of the present invention. For example, the dielectric layerstack may include a first anti-ferroelectric layer, a secondanti-ferroelectric layer, and a ferroelectric layer disposed between thefirst anti-ferroelectric layer and the second anti-ferroelectric layer.

The dielectric layer stack in accordance with the above-describedembodiments of the present invention may be applied to an embedded DRAM.For example, the embedded DRAM may include a logic circuit and acapacitor, and the capacitor of the embedded DRAM may include a lowerelectrode, a dielectric layer stack, and an upper electrode. Thedielectric layer stack of the capacitor of the embedded DRAM may includeone among the dielectric layer stacks of the above-described embodimentsof the present invention. For example, the dielectric layer stack mayinclude a first anti-ferroelectric layer, a second anti-ferroelectriclayer, and a ferroelectric layer disposed between the firstanti-ferroelectric layer and the second anti-ferroelectric layer.

The dielectric layer stack in accordance with the above-describedembodiments of the present invention may be applied to a 3D NAND(Three-Dimensional NAND). For example, the 3D NAND may include adielectric layer stack including a pillar-type channel layer, a wordline surrounding the pillar-type channel layer, and a tunnel dielectriclayer between the pillar-type channel layer and the word line. At leastthe tunnel dielectric layer of the dielectric layer stack of the 3D NANDmay include at least one among the first anti-ferroelectric layer, thesecond anti-ferroelectric layer, and the ferroelectric layer of theabove-described embodiments of the present invention.

According to the embodiment of the present invention, it is possible tocontrol the switching voltage, capacitance, and polarization of adielectric layer stack by controlling the composition ratio between aferroelectric material and an anti-ferroelectric material. Accordingly,a volatile memory may be implemented.

While the present invention has been described with respect to specificembodiments, it will be apparent to those skilled in the art thatvarious changes and modifications may be made without departing from thespirit and scope of the invention as defined in the following claims.

What is claimed is:
 1. A semiconductor device comprising: a firstelectrode; a second electrode; an alternating stack that is positionedbetween the first electrode and the second electrode, the alternatingstack including a plurality of dielectric layer stacks and a pluralityof leakage blocking layers that are alternately stacked, an interfacelayer disposed between the second electrode and the alternating stack;and an additional interface layer disposed between the first electrodeand the alternating stack, wherein each of the dielectric layer stacksincludes a first anti-ferroelectric layer, a second anti-ferroelectriclayer, and a ferroelectric layer disposed between the firstanti-ferroelectric layer and the second anti-ferroelectric layer.
 2. Thesemiconductor device of claim 1, wherein the first anti-ferroelectriclayer, the ferroelectric layer, and the second anti-ferroelectric layerare vertically arranged between the first electrode and the secondelectrode.
 3. The semiconductor device of claim 1, wherein the firstanti-ferroelectric layer and the second anti-ferroelectric layer includean anti-ferroelectric hafnium zirconium oxide, and the ferroelectriclayer includes a ferroelectric hafnium zirconium oxide.
 4. Thesemiconductor device of claim 1, wherein the first anti-ferroelectriclayer and the second anti-ferroelectric layer include a hafniumzirconium oxide having a zirconium content greater than a hafniumcontent.
 5. The semiconductor device of claim 1, wherein theferroelectric layer includes a hafnium zirconium oxide whose hafniumcontent and zirconium content are the same.
 6. The semiconductor deviceof claim 1, wherein the first anti-ferroelectric layer and the secondanti-ferroelectric layer include PbZrO₃, PbHfO₃, PbMgWO₃, PbZrTiO₃,BiNaTiO₃ or NaNbO₃.
 7. The semiconductor device of claim 1, wherein theferroelectric layer includes BaTiO₃, PbTiO₃, BiFeO₃, SrTiO₃, PbMgNdO₃,PbMgNbTiO₃, PbZrNbTiO₃, PbZrTiO₃, KNbO₃, LiNbO₃, GeTe, LiTaO₃, KNaNbO₃,or BaSrTiO₃.
 8. The semiconductor device of claim 1, wherein theinterface layer includes a material that is reduced prior to thedielectric layer stack.
 9. The semiconductor device of claim 1, whereinthe interface layer and the additional interface layer include amaterial having a greater electronegativity than the first and secondanti-ferroelectric layers and the ferroelectric layer.
 10. Thesemiconductor device of claim 1, wherein the interface layer and theadditional interface layer include titanium oxide, tantalum oxide,niobium oxide, or tin oxide.
 11. The semiconductor device of claim 1,wherein the first electrode includes a cylinder shape, a pillar shape,or a hybrid pillar-cylinder.
 12. The semiconductor device of claim 1,further comprising: a semiconductor substrate including a first dopedregion and a second doped region; a word line buried in a semiconductorsubstrate between the first doped region and the second doped region; abit line formed over the word line and coupled to the first dopedregion; and a storage node contact plug coupled to the second dopedregion, wherein the first electrode is electrically connected to thestorage node contact plug.
 13. The semiconductor device of claim 1,wherein the first electrode, the alternating stack, and the secondelectrode form a Dynamic Random Access Memory (DRAM) capacitor.
 14. Thesemiconductor device of claim 1, wherein each of the leakage blockinglayers includes a material having a higher energy band gap than thedielectric stack.
 15. The semiconductor device of claim 1, wherein eachof the leakage blocking layers includes a material having a higherenergy band gap than the first anti-ferroelectric layer, the secondanti-ferroelectric layer, and the ferroelectric layer.
 16. Thesemiconductor device of claim 1, wherein each of the leakage blockinglayers includes aluminum oxide or beryllium oxide.
 17. The semiconductordevice of claim 1, wherein the interface layer includes a stack ofmolybdenum and molybdenum nitride (Mo/MoN) or a stack of tungsten andtungsten nitride (W/WN).
 18. The semiconductor device of claim 1,further comprising: a supporter for supporting of the first electrode.